Power Integrity Simulation for Large DRAM designs using Totem-SC

Power Integrity(PI) simulation of DRAM designs require simulation tools that can handle million order transistor count, simulate long duration vectors, model circuits such has LDO, charge pumps specialized capacitors, header and footer switches. These simulations have to complete in reasonable time to help design teams detect, assess and fix PDN weakness. DRAM design companies have made attempts to run fast spice based power integrity simulations to help address this, however the turnaround time for typical 16GB DRAM designs with fast spice can be several days leading to long project execution cycles. Totem-SC, built on Ansys Bigdata SeaScape platform, is designed to process and model design data in distributed mode. It embeds an iterative linear matrix solver that helps run power integrity simulation for million order transistor designs in about a day while retaining similar accuracy as its predecessor Ansys Totem. Totem-SC models active devices, special circuits like LDO,charge pumps, header, footer power gating circuits as linear circuit model that is compatible to linear matrix solver. Totem-SC can consume device currents from schematic netlist based external spice simulations done on slices/full DRAM design. It also offers flexibility of assigning transient currents and intentional cap to regions of design for which spice demand currents are not available. In this presentation, PI simulation workflow being deployed to SkHynix is described. This workflow highlights PI simulation data preparation for large DDR, GDDR designs that needs to be simulated for 100s of ns. Linear circuit modelling techniques for LDO, charge pumps specialized capacitors, header and footer switches are described. Comparison of performance and simulation result quality against Ansys Totem is presented.