An automatic convergence-oriented mesh refinement flow for 3D-IC system

Nowadays, the semiconductor industry has already evolute down to 5nm or even 1nm process to get the best performance. However, it’s already seen a big challenge in pushing this beyond only by shrinking the size of the transistor. Migrating traditional 2D/2.5D IC into 3D stacking IC system is becoming common sense of semiconductor industry. 3D-IC system has shorter electrical connections, lower parasitic effect and many advantages, which is the dream of chip designers. However, on the other hand, it has much higher power density, much more complicated stacking structures and more coupling effect, which is a nightmare for thermal engineers. To thermally sign-off 3D-IC design relies on accurate temperature simulation result for each die. Traditional approaches encounter capacity/performance vs accuracy bottlenecks and hence are limited to small die sizes. Trying to adopt the same approach to 3D-IC structures, containing multiple dies, with each die being large (like interposer) is an impossible task. We present a novel solution to solve this bottleneck by an automatic convergence-oriented mesh refinement flow that can better serve modern 3D-IC systems. In this flow, it will have quick estimation on the initial meshing for all the components in the system including active & passive die and other components included as well. Then it will smartly add finer meshing on the area where it’s needed and rollback the unnecessary mesh refinement if such scenario is detected. After several iterations, the optimized meshing could be converged to get the best trade-off between capacity/performance vs accuracy, which makes the thermal sign-off for large 3D-IC system to be a mission possible.