Leveraging Scan Vectorless for ATPG Robustness

Typically, IR drop analysis targeted only for the functional mode use cases. ATPG modes, especially stuck-at-fault analysis in Design for Testability (DFT) is not considered for DvD as the frequency of operation is lower. However, in scan mode, simultaneous switching of large number of registers give rise to high peak current and di/dt effects which, when coupled with package inductance is bound to introduce significant IR drop issues. It also captures secondary effects such as unintentional switching in the data path and combinational logic downstream of the flops. VCD based analysis is the most common method to annotate the activity on the scan flops. However, securing the VCDs for multiple cores and the duration of VCDs to cover switching activity of all scan chains is a huge challenge. This paper talks about the work done to perform vector less scan mode analysis, using an early-stage design data without the need of gate VCD which is available very late in the design stage. This RedHawk-SC based scan vector less flow demonstrates a unified setup which provides seamless method to consume scan chain configuration along with the pattern annotation without involving heavy vector generation process. The irdrop results from this method correlates very well with the actual VCD based dynamic irdrop analysis.