Early Clock Tree Power Correlation at SOC: A Case Study

The clock tree power is one of the critical aspects to be estimated and analyzed for an SoC, as the clock network power contributes to major share in overall power of the chip. Typically, clock power estimations and analysis is performed at gate level which is late in the cycle (CTS stage), which would not provide any room for design optimization due to stringent timelines of SOC execution. So, it will be very useful to have early estimation of power on RTL, which provides more scope to optimize the design for power, much earlier in the design cycle. This paper discusses the advantages and challenges of extracting clock tree power on RTL by deploying PowerArtist tool and finding out the areas of improvement in design which helps in optimizing the design for better quality in terms of power. This paper also discusses the challenges running the PowerArtist at SOC level and provides suggestions to optimize the runtimes and report analysis.